International Journal of Engineering, Science and Mathematics
(IJMRA Publications)-
Peer Reviewed Refereed Journal


Pages: 146-152

Date of Publication: 24-Dec-2017


Author: 1. Dr.DeepikaPatnaik, 2. Dr.S.S.Nayak, 3. Dr. Banitamani Mallik

Category: Engineering, Science and Mathematics

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In this paper, we have suggested a simple scheme for prime-factor decomposition of Inverse Discrete Cosine Transform (IDCT) and systolic mesh architecture for its implementation. It is interesting to note that the transposition of the intermediate matrix is avoided in this structure by orthogonal processing during the pair of matrix multiplication i.e., if the processing for the first matrix multiplication takes place along X-direction, the processing for the second matrix multiplication is carried out along Y-direction. Due to this feature, the structure is highly compact, offers saving for transposition hardware and at the same time yields high throughput with less latency.

Keywords: Inverse Discrete cosine Transform (IDCT), Prime-factor decomposition, VLSI, Systolic architecture, Orthogonal processing.